CTC++ Coverage Report

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True	False	-	Line	Source

			1	/*
			2	* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
			3	*
			4	* This is an 64bit optimized version that always keeps the full mmconfig
			5	* space mapped. This allows lockless config space operation.
			6	*/
			7
			8	#include <linux/pci.h>
			9	#include <linux/init.h>
			10	#include <linux/acpi.h>
			11	#include <linux/bitmap.h>
			12	#include "pci.h"
			13
			14	#define MMCONFIG_APER_SIZE (25610241024)
			15
			16	static DECLARE_BITMAP(fallback_slots, 32);
			17
			18	/* Static virtual mapping of the MMCONFIG aperture */
			19	struct mmcfg_virt {
			20	struct acpi_table_mcfg_config *cfg;
			21	char __iomem *virt;
			22	};
			23	static struct mmcfg_virt *pci_mmcfg_virt;
			24

0	0	-	25	static char __iomem *get_virt(unsigned int seg, unsigned bus)
			26	{
			27	int cfg_num = -1;
			28	struct acpi_table_mcfg_config *cfg;
			29
0	0	-	30	while (1) {
			31	++cfg_num;
0	0	-	32	if (cfg_num >= pci_mmcfg_config_num)
0		-	33	break;
			34	cfg = pci_mmcfg_virt[cfg_num].cfg;
0	0	-	35	if (cfg->pci_segment_group_number != seg)
0		-	36	continue;
			37	if ((cfg->start_bus_number <= bus) &&
0	0	-	38	(cfg->end_bus_number >= bus))
0		-	38	(T) && (T)
	0	-	38	(T) && (F)
	0	-	38	(F) && (_)
0		-	39	return pci_mmcfg_virt[cfg_num].virt;
			40	}
			41
			42	/* Handle more broken MCFG tables on Asus etc.
			43	They only contain a single entry for bus 0-0. Assume
			44	this applies to all busses. */
			45	cfg = &pci_mmcfg_config[0];
			46	if (pci_mmcfg_config_num == 1 &&
			47	cfg->pci_segment_group_number == 0 &&
0	0	-	48	(cfg->start_bus_number \| cfg->end_bus_number) == 0)
0		-	48	T && T && T
	0	-	48	T && T && F
	0	-	48	T && F && _
	0	-	48	F && _ && _
0		-	49	return pci_mmcfg_virt[0].virt;
			50
			51	/* Fall back to type 0 */
0		-	52	return NULL;
			53	}
			54

0	0	-	55	static char __iomem *pci_dev_base(unsigned int seg, unsigned int bus, unsigned int devfn)
			56	{
			57	char __iomem *addr;
0	0	-	58	if (seg == 0 && bus == 0 && test_bit(PCI_SLOT(devfn), &fallback_slots))
0		-	58	T && T && (T)
	0	-	58	T && T && (F)
	0	-	58	T && F && (_)
	0	-	58	F && _ && (_)
0	0	-	58	ternary-?: __builtin_constant_p ( ( ( ( devfn ..
0		-	59	return NULL;
			60	addr = get_virt(seg, bus);
0	0	-	61	if (!addr)
0		-	62	return NULL;
0		-	63	return addr + ((bus << 20) \| (devfn << 12));
			64	}
			65

0	0	-	66	static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
			67	unsigned int devfn, int reg, int len, u32 *value)
			68	{
			69	char __iomem *addr;
			70
			71	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
0	0	-	72	if (unlikely(!value \|\| (bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
0		-	73	return -EINVAL;
			74
			75	addr = pci_dev_base(seg, bus, devfn);
0	0	-	76	if (!addr)
0		-	77	return pci_conf1_read(seg,bus,devfn,reg,len,value);
			78
			79	switch (len) {
0		-	80	case 1:
			81	*value = readb(addr + reg);
0		-	82	break;
0		-	83	case 2:
			84	*value = readw(addr + reg);
0		-	85	break;
0		-	86	case 4:
			87	*value = readl(addr + reg);
0		-	88	break;
			89	}
			90
0		-	91	return 0;
			92	}
			93

0	0	-	94	static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
			95	unsigned int devfn, int reg, int len, u32 value)
			96	{
			97	char __iomem *addr;
			98
			99	/* Why do we have this when nobody checks it. How about a BUG()!? -AK */
0	0	-	100	if (unlikely((bus > 255) \|\| (devfn > 255) \|\| (reg > 4095)))
0		-	101	return -EINVAL;
			102
			103	addr = pci_dev_base(seg, bus, devfn);
0	0	-	104	if (!addr)
0		-	105	return pci_conf1_write(seg,bus,devfn,reg,len,value);
			106
			107	switch (len) {
0		-	108	case 1:
			109	writeb(value, addr + reg);
0		-	110	break;
0		-	111	case 2:
			112	writew(value, addr + reg);
0		-	113	break;
0		-	114	case 4:
			115	writel(value, addr + reg);
0		-	116	break;
			117	}
			118
0		-	119	return 0;
			120	}
			121
			122	static struct pci_raw_ops pci_mmcfg = {
			123	.read = pci_mmcfg_read,
			124	.write = pci_mmcfg_write,
			125	};
			126
			127	/* K8 systems have some devices (typically in the builtin northbridge)
			128	that are only accessible using type1
			129	Normally this can be expressed in the MCFG by not listing them
			130	and assigning suitable _SEGs, but this isn't implemented in some BIOS.
			131	Instead try to discover all devices on bus 0 that are unreachable using MM
			132	and fallback for them.
			133	We only do this for bus 0/seg 0 */

0	0	-	134	static __init void unreachable_devices(void)
			135	{
			136	int i;
0	0	-	137	for (i = 0; i < 32; i++) {
			138	u32 val1;
			139	char __iomem *addr;
			140
			141	pci_conf1_read(0, 0, PCI_DEVFN(i,0), 0, 4, &val1);
0	0	-	142	if (val1 == 0xffffffff)
0		-	143	continue;
			144	addr = pci_dev_base(0, 0, PCI_DEVFN(i, 0));
0	0	-	145	if (addr == NULL\|\| readl(addr) != val1) {
0		-	145	T \|\| _
0		-	145	F \|\| T
	0	-	145	F \|\| F
			146	set_bit(i, &fallback_slots);
			147	}
			148	}
			149	}
			150

6	0		151	static int __init pci_mmcfg_init(void)
			152	{
			153	int i;
			154
0	6	-	155	if ((pci_probe & PCI_PROBE_MMCONF) == 0)
0		-	156	return 0;
			157
			158	acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
			159	if ((pci_mmcfg_config_num == 0) \|\|
			160	(pci_mmcfg_config == NULL) \|\|
6	0	-	161	(pci_mmcfg_config[0].base_address == 0))
6			161	(T) \|\| (_) \|\| (_)
0		-	161	(F) \|\| (T) \|\| (_)
0		-	161	(F) \|\| (F) \|\| (T)
	0	-	161	(F) \|\| (F) \|\| (F)
6			162	return 0;
			163
			164	/* RED-PEN i386 doesn't do _nocache right now */
			165	pci_mmcfg_virt = kmalloc(sizeof(pci_mmcfg_virt) pci_mmcfg_config_num, GFP_KERNEL);
0	0	-	166	if (pci_mmcfg_virt == NULL) {
			167	printk("PCI: Can not allocate memory for mmconfig structures\n");
0		-	168	return 0;
			169	}
0	0	-	170	for (i = 0; i < pci_mmcfg_config_num; ++i) {
			171	pci_mmcfg_virt[i].cfg = &pci_mmcfg_config[i];
			172	pci_mmcfg_virt[i].virt = ioremap_nocache(pci_mmcfg_config[i].base_address, MMCONFIG_APER_SIZE);
0	0	-	173	if (!pci_mmcfg_virt[i].virt) {
			174	printk("PCI: Cannot map mmconfig aperture for segment %d\n",
			175	pci_mmcfg_config[i].pci_segment_group_number);
0		-	176	return 0;
			177	}
			178	printk(KERN_INFO "PCI: Using MMCONFIG at %x\n", pci_mmcfg_config[i].base_address);
			179	}
			180
			181	unreachable_devices();
			182
			183	raw_pci_ops = &pci_mmcfg;
			184	pci_probe = (pci_probe & ~PCI_PROBE_MASK) \| PCI_PROBE_MMCONF;
			185
0		-	186	return 0;
			187	}
			188
			189	arch_initcall(pci_mmcfg_init);
***TER 5% (5/96) of SOURCE FILE mmconfig.c