CTC++ Coverage Report

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			1	/*
			2	* Low-Level PCI Access for i386 machines
			3	*
			4	* Copyright 1993, 1994 Drew Eckhardt
			5	* Visionary Computing
			6	* (Unix and Linux consulting and custom programming)
			7	* Drew@Colorado.EDU
			8	* +1 (303) 786-7975
			9	*
			10	* Drew's work was sponsored by:
			11	* iX Multiuser Multitasking Magazine
			12	* Hannover, Germany
			13	* hm@ix.de
			14	*
			15	* Copyright 1997--2000 Martin Mares <mj@ucw.cz>
			16	*
			17	* For more information, please consult the following manuals (look at
			18	* http://www.pcisig.com/ for how to get them):
			19	*
			20	* PCI BIOS Specification
			21	* PCI Local Bus Specification
			22	* PCI to PCI Bridge Specification
			23	* PCI System Design Guide
			24	*
			25	*/
			26
			27	#include <linux/types.h>
			28	#include <linux/kernel.h>
			29	#include <linux/pci.h>
			30	#include <linux/init.h>
			31	#include <linux/ioport.h>
			32	#include <linux/errno.h>
			33
			34	#include "pci.h"
			35
			36	/*
			37	* We need to avoid collisions with `mirrored' VGA ports
			38	* and other strange ISA hardware, so we always want the
			39	* addresses to be allocated in the 0x000-0x0ff region
			40	* modulo 0x400.
			41	*
			42	* Why? Because some silly external IO cards only decode
			43	* the low 10 bits of the IO address. The 0x00-0xff region
			44	* is reserved for motherboard devices that decode all 16
			45	* bits, so it's ok to allocate at, say, 0x2800-0x28ff,
			46	* but we want to try to avoid allocating at 0x2900-0x2bff
			47	* which might have be mirrored at 0x0100-0x03ff..
			48	*/
			49	void

450	450		50	pcibios_align_resource(void data, struct resource res,
			51	unsigned long size, unsigned long align)
			52	{
228	222		53	if (res->flags & IORESOURCE_IO) {
			54	unsigned long start = res->start;
			55
78	150		56	if (start & 0x300) {
			57	start = (start + 0x3ff) & ~0x3ff;
			58	res->start = start;
			59	}
			60	}
			61	}
			62
			63
			64	/*
			65	* Handle resources of PCI devices. If the world were perfect, we could
			66	* just allocate all the resource regions and do nothing more. It isn't.
			67	* On the other hand, we cannot just re-allocate all devices, as it would
			68	* require us to know lots of host bridge internals. So we attempt to
			69	* keep as much of the original configuration as possible, but tweak it
			70	* when it's found to be wrong.
			71	*
			72	* Known BIOS problems we have to work around:
			73	* - I/O or memory regions not configured
			74	* - regions configured, but not enabled in the command register
			75	* - bogus I/O addresses above 64K used
			76	* - expansion ROMs left enabled (this may sound harmless, but given
			77	* the fact the PCI specs explicitly allow address decoders to be
			78	* shared between expansion ROMs and other resource regions, it's
			79	* at least dangerous)
			80	*
			81	* Our solution:
			82	* (1) Allocate resources for all buses behind PCI-to-PCI bridges.
			83	* This gives us fixed barriers on where we can allocate.
			84	* (2) Allocate resources for all enabled devices. If there is
			85	* a collision, just mark the resource as unallocated. Also
			86	* disable expansion ROMs during this step.
			87	* (3) Try to allocate resources for disabled devices. If the
			88	* resources were assigned correctly, everything goes well,
			89	* if they weren't, they won't disturb allocation of other
			90	* resources.
			91	* (4) Assign new addresses to resources which were either
			92	* not configured at all or misconfigured. If explicitly
			93	* requested by the user, configure expansion ROM address
			94	* as well.
			95	*/
			96

24	24		97	static void __init pcibios_allocate_bus_resources(struct list_head *bus_list)
			98	{
			99	struct pci_bus *bus;
			100	struct pci_dev *dev;
			101	int idx;
			102	struct resource r, pr;
			103
			104	/* Depth-First Search on bus tree */
18	24		105	list_for_each_entry(bus, bus_list, node) {
12	6		106	if ((dev = bus->self)) {
48	12		107	for (idx = PCI_BRIDGE_RESOURCES; idx < PCI_NUM_RESOURCES; idx++) {
			108	r = &dev->resource[idx];
30	18		109	if (!r->flags)
30			110	continue;
			111	pr = pci_find_parent_resource(dev, r);
0	18	-	112	if (!r->start \|\| !pr \|\| request_resource(pr, r) < 0) {
0		-	112	T \|\| _ \|\| _
0		-	112	F \|\| T \|\| _
0		-	112	F \|\| F \|\| T
	18		112	F \|\| F \|\| F
			113	printk(KERN_ERR "PCI: Cannot allocate resource region %d of bridge %s\n", idx, pci_name(dev));
			114	/* Something is wrong with the region.
			115	Invalidate the resource to prevent child
			116	resource allocations in this range. */
			117	r->flags = 0;
			118	}
			119	}
			120	}
			121	pcibios_allocate_bus_resources(&bus->children);
			122	}
			123	}
			124

12	12		125	static void __init pcibios_allocate_resources(int pass)
			126	{
			127	struct pci_dev *dev = NULL;
			128	int idx, disabled;
			129	u16 command;
			130	struct resource r, pr;
			131
228	12		132	for_each_pci_dev(dev) {
			133	pci_read_config_word(dev, PCI_COMMAND, &command);
1368	228		134	for(idx = 0; idx < 6; idx++) {
			135	r = &dev->resource[idx];
90	1278		136	if (r->parent) /* Already allocated */
90			137	continue;
1188	90		138	if (!r->start) /* Address not assigned at all */
1188			139	continue;
42	48		140	if (r->flags & IORESOURCE_IO)
			141	disabled = !(command & PCI_COMMAND_IO);
			142	else
			143	disabled = !(command & PCI_COMMAND_MEMORY);
90	0	-	144	if (pass == disabled) {
			145	DBG("PCI: Resource %08lx-%08lx (f=%lx, d=%d, p=%d)\n",
			146	r->start, r->end, r->flags, disabled, pass);
			147	pr = pci_find_parent_resource(dev, r);
0	90	-	148	if (!pr \|\| request_resource(pr, r) < 0) {
0		-	148	T \|\| _
0		-	148	F \|\| T
	90		148	F \|\| F
			149	printk(KERN_ERR "PCI: Cannot allocate resource region %d of device %s\n", idx, pci_name(dev));
			150	/* We'll assign a new address later */
			151	r->end -= r->start;
			152	r->start = 0;
			153	}
			154	}
			155	}
114	114		156	if (!pass) {
			157	r = &dev->resource[PCI_ROM_RESOURCE];
0	114	-	158	if (r->flags & IORESOURCE_ROM_ENABLE) {
			159	/* Turn the ROM off, leave the resource region, but keep it unregistered. */
			160	u32 reg;
			161	DBG("PCI: Switching off ROM of %s\n", pci_name(dev));
			162	r->flags &= ~IORESOURCE_ROM_ENABLE;
			163	pci_read_config_dword(dev, dev->rom_base_reg, &reg);
			164	pci_write_config_dword(dev, dev->rom_base_reg, reg & ~PCI_ROM_ADDRESS_ENABLE);
			165	}
			166	}
			167	}
			168	}
			169

6	0		170	static int __init pcibios_assign_resources(void)
			171	{
			172	struct pci_dev *dev = NULL;
			173	struct resource r, pr;
			174
6	0	-	175	if (!(pci_probe & PCI_ASSIGN_ROMS)) {
			176	/* Try to use BIOS settings for ROMs, otherwise let
			177	pci_assign_unassigned_resources() allocate the new
			178	addresses. */
114	6		179	for_each_pci_dev(dev) {
			180	r = &dev->resource[PCI_ROM_RESOURCE];
114	0	-	181	if (!r->flags \|\| !r->start)
108			181	T \|\| _
6			181	F \|\| T
	0	-	181	F \|\| F
114			182	continue;
			183	pr = pci_find_parent_resource(dev, r);
0	0	-	184	if (!pr \|\| request_resource(pr, r) < 0) {
0		-	184	T \|\| _
0		-	184	F \|\| T
	0	-	184	F \|\| F
			185	r->end -= r->start;
			186	r->start = 0;
			187	}
			188	}
			189	}
			190
			191	pci_assign_unassigned_resources();
			192
6			193	return 0;
			194	}
			195

6	6		196	void __init pcibios_resource_survey(void)
			197	{
			198	DBG("PCI: Allocating resources\n");
			199	pcibios_allocate_bus_resources(&pci_root_buses);
			200	pcibios_allocate_resources(0);
			201	pcibios_allocate_resources(1);
			202	}
			203
			204	/**
			205	* called in fs_initcall (one below subsys_initcall),
			206	* give a chance for motherboard reserve resources
			207	*/
			208	fs_initcall(pcibios_assign_resources);
			209

78	0		210	int pcibios_enable_resources(struct pci_dev *dev, int mask)
			211	{
			212	u16 cmd, old_cmd;
			213	int idx;
			214	struct resource *r;
			215
			216	pci_read_config_word(dev, PCI_COMMAND, &cmd);
			217	old_cmd = cmd;
858	78		218	for(idx = 0; idx < PCI_NUM_RESOURCES; idx++) {
			219	/* Only set up the requested stuff */
0	858	-	220	if (!(mask & (1<<idx)))
0		-	221	continue;
			222
			223	r = &dev->resource[idx];
690	168		224	if (!(r->flags & (IORESOURCE_IO \| IORESOURCE_MEM)))
690			225	continue;
			226	if ((idx == PCI_ROM_RESOURCE) &&
6	162		227	(!(r->flags & IORESOURCE_ROM_ENABLE)))
6			227	(T) && (!(F))
	0	-	227	(T) && (!(T))
	162		227	(F) && (!(_))
6			228	continue;
0	162	-	229	if (!r->start && r->end) {
0		-	229	T && T
	0	-	229	T && F
	162		229	F && _
			230	printk(KERN_ERR "PCI: Device %s not available because of resource collisions\n", pci_name(dev));
0		-	231	return -EINVAL;
			232	}
78	84		233	if (r->flags & IORESOURCE_IO)
			234	cmd \|= PCI_COMMAND_IO;
84	78		235	if (r->flags & IORESOURCE_MEM)
			236	cmd \|= PCI_COMMAND_MEMORY;
			237	}
0	78	-	238	if (cmd != old_cmd) {
			239	printk("PCI: Enabling device %s (%04x -> %04x)\n", pci_name(dev), old_cmd, cmd);
			240	pci_write_config_word(dev, PCI_COMMAND, cmd);
			241	}
78			242	return 0;
			243	}
			244
			245	/*
			246	* If we set up a device for bus mastering, we need to check the latency
			247	* timer as certain crappy BIOSes forget to set it properly.
			248	*/
			249	unsigned int pcibios_max_latency = 255;
			250

54	18		251	void pcibios_set_master(struct pci_dev *dev)
			252	{
			253	u8 lat;
			254	pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
18	36		255	if (lat < 16)
			256	lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
18	0	-	256	ternary-?: ( 64 <= pcibios_max_latency )
0	36	-	257	else if (lat > pcibios_max_latency)
			258	lat = pcibios_max_latency;
			259	else
36			260	return;
			261	printk(KERN_DEBUG "PCI: Setting latency timer of device %s to %d\n", pci_name(dev), lat);
			262	pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
			263	}
			264

0	0	-	265	int pci_mmap_page_range(struct pci_dev dev, struct vm_area_struct vma,
			266	enum pci_mmap_state mmap_state, int write_combine)
			267	{
			268	unsigned long prot;
			269
			270	/* I/O space cannot be accessed via normal processor loads and
			271	* stores on this platform.
			272	*/
0	0	-	273	if (mmap_state == pci_mmap_io)
0		-	274	return -EINVAL;
			275
			276	/* Leave vm_pgoff as-is, the PCI space address is the physical
			277	* address on this platform.
			278	*/
			279	vma->vm_flags \|= (VM_SHM \| VM_LOCKED \| VM_IO);
			280
			281	prot = pgprot_val(vma->vm_page_prot);
0	0	-	282	if (boot_cpu_data.x86 > 3)
			283	prot \|= _PAGE_PCD \| _PAGE_PWT;
			284	vma->vm_page_prot = __pgprot(prot);
			285
			286	/* Write-combine setting is ignored, it is changed via the mtrr
			287	* interfaces on this platform.
			288	*/
0	0	-	289	if (io_remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
			290	vma->vm_end - vma->vm_start,
			291	vma->vm_page_prot))
0		-	292	return -EAGAIN;
			293
0		-	294	return 0;
			295	}
***TER 66% (72/109) of SOURCE FILE i386.c