| Start/ | End/ | |||
| True | False | - | Line | Source |
| 1 | /* | |||
| 2 | * linux/drivers/char/8250.c | |||
| 3 | * | |||
| 4 | * Driver for 8250/16550-type serial ports | |||
| 5 | * | |||
| 6 | * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. | |||
| 7 | * | |||
| 8 | * Copyright (C) 2001 Russell King. | |||
| 9 | * | |||
| 10 | * This program is free software; you can redistribute it and/or modify | |||
| 11 | * it under the terms of the GNU General Public License as published by | |||
| 12 | * the Free Software Foundation; either version 2 of the License, or | |||
| 13 | * (at your option) any later version. | |||
| 14 | * | |||
| 15 | * $Id: 8250.c,v 1.90 2002/07/28 10:03:27 rmk Exp $ | |||
| 16 | * | |||
| 17 | * A note about mapbase / membase | |||
| 18 | * | |||
| 19 | * mapbase is the physical address of the IO port. | |||
| 20 | * membase is an 'ioremapped' cookie. | |||
| 21 | */ | |||
| 22 | #include <linux/config.h> | |||
| 23 | ||||
| 24 | #if defined(CONFIG_SERIAL_8250_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) | |||
| 25 | #define SUPPORT_SYSRQ | |||
| 26 | #endif | |||
| 27 | ||||
| 28 | #include <linux/module.h> | |||
| 29 | #include <linux/moduleparam.h> | |||
| 30 | #include <linux/ioport.h> | |||
| 31 | #include <linux/init.h> | |||
| 32 | #include <linux/console.h> | |||
| 33 | #include <linux/sysrq.h> | |||
| 34 | #include <linux/delay.h> | |||
| 35 | #include <linux/platform_device.h> | |||
| 36 | #include <linux/tty.h> | |||
| 37 | #include <linux/tty_flip.h> | |||
| 38 | #include <linux/serial_reg.h> | |||
| 39 | #include <linux/serial_core.h> | |||
| 40 | #include <linux/serial.h> | |||
| 41 | #include <linux/serial_8250.h> | |||
| 42 | #include <linux/nmi.h> | |||
| 43 | #include <linux/mutex.h> | |||
| 44 | ||||
| 45 | #include <asm/io.h> | |||
| 46 | #include <asm/irq.h> | |||
| 47 | ||||
| 48 | #include "8250.h" | |||
| 49 | ||||
| 50 | /* | |||
| 51 | * Configuration: | |||
| 52 | * share_irqs - whether we pass SA_SHIRQ to request_irq(). This option | |||
| 53 | * is unsafe when used on edge-triggered interrupts. | |||
| 54 | */ | |||
| 55 | static unsigned int share_irqs = SERIAL8250_SHARE_IRQS; | |||
| 56 | ||||
| 57 | static unsigned int nr_uarts = CONFIG_SERIAL_8250_RUNTIME_UARTS; | |||
| 58 | ||||
| 59 | /* | |||
| 60 | * Debugging. | |||
| 61 | */ | |||
| 62 | #if 0 | |||
| 63 | #define DEBUG_AUTOCONF(fmt...) printk(fmt) | |||
| 64 | #else | |||
| 65 | #define DEBUG_AUTOCONF(fmt...) do { } while (0) | |||
| 66 | #endif | |||
| 67 | ||||
| 68 | #if 0 | |||
| 69 | #define DEBUG_INTR(fmt...) printk(fmt) | |||
| 70 | #else | |||
| 71 | #define DEBUG_INTR(fmt...) do { } while (0) | |||
| 72 | #endif | |||
| 73 | ||||
| 74 | #define PASS_LIMIT 256 | |||
| 75 | ||||
| 76 | /* | |||
| 77 | * We default to IRQ0 for the "no irq" hack. Some | |||
| 78 | * machine types want others as well - they're free | |||
| 79 | * to redefine this in their header file. | |||
| 80 | */ | |||
| 81 | #define is_real_interrupt(irq) ((irq) != 0) | |||
| 82 | ||||
| 83 | #ifdef CONFIG_SERIAL_8250_DETECT_IRQ | |||
| 84 | #define CONFIG_SERIAL_DETECT_IRQ 1 | |||
| 85 | #endif | |||
| 86 | #ifdef CONFIG_SERIAL_8250_MANY_PORTS | |||
| 87 | #define CONFIG_SERIAL_MANY_PORTS 1 | |||
| 88 | #endif | |||
| 89 | ||||
| 90 | /* | |||
| 91 | * HUB6 is always on. This will be removed once the header | |||
| 92 | * files have been cleaned. | |||
| 93 | */ | |||
| 94 | #define CONFIG_HUB6 1 | |||
| 95 | ||||
| 96 | #include <asm/serial.h> | |||
| 97 | ||||
| 98 | /* | |||
| 99 | * SERIAL_PORT_DFNS tells us about built-in ports that have no | |||
| 100 | * standard enumeration mechanism. Platforms that can find all | |||
| 101 | * serial ports via mechanisms like ACPI or PCI need not supply it. | |||
| 102 | */ | |||
| 103 | #ifndef SERIAL_PORT_DFNS | |||
| 104 | #define SERIAL_PORT_DFNS | |||
| 105 | #endif | |||
| 106 | ||||
| 107 | static const struct old_serial_port old_serial_port[] = { | |||
| 108 | SERIAL_PORT_DFNS /* defined in asm/serial.h */ | |||
| 109 | }; | |||
| 110 | ||||
| 111 | #define UART_NR CONFIG_SERIAL_8250_NR_UARTS | |||
| 112 | ||||
| 113 | #ifdef CONFIG_SERIAL_8250_RSA | |||
| 114 | ||||
| 115 | #define PORT_RSA_MAX 4 | |||
| 116 | static unsigned long probe_rsa[PORT_RSA_MAX]; | |||
| 117 | static unsigned int probe_rsa_count; | |||
| 118 | #endif /* CONFIG_SERIAL_8250_RSA */ | |||
| 119 | ||||
| 120 | struct uart_8250_port { | |||
| 121 | struct uart_port port; | |||
| 122 | struct timer_list timer; /* "no irq" timer */ | |||
| 123 | struct list_head list; /* ports on this IRQ */ | |||
| 124 | unsigned short capabilities; /* port capabilities */ | |||
| 125 | unsigned short bugs; /* port bugs */ | |||
| 126 | unsigned int tx_loadsz; /* transmit fifo load size */ | |||
| 127 | unsigned char acr; | |||
| 128 | unsigned char ier; | |||
| 129 | unsigned char lcr; | |||
| 130 | unsigned char mcr; | |||
| 131 | unsigned char mcr_mask; /* mask of user bits */ | |||
| 132 | unsigned char mcr_force; /* mask of forced bits */ | |||
| 133 | unsigned char lsr_break_flag; | |||
| 134 | ||||
| 135 | /* | |||
| 136 | * We provide a per-port pm hook. | |||
| 137 | */ | |||
| 138 | void (*pm)(struct uart_port *port, | |||
| 139 | unsigned int state, unsigned int old); | |||
| 140 | }; | |||
| 141 | ||||
| 142 | struct irq_info { | |||
| 143 | spinlock_t lock; | |||
| 144 | struct list_head *head; | |||
| 145 | }; | |||
| 146 | ||||
| 147 | static struct irq_info irq_lists[NR_IRQS]; | |||
| 148 | ||||
| 149 | /* | |||
| 150 | * Here we define the default xmit fifo size used for each type of UART. | |||
| 151 | */ | |||
| 152 | static const struct serial8250_config uart_config[] = { | |||
| 153 | [PORT_UNKNOWN] = { | |||
| 154 | .name = "unknown", | |||
| 155 | .fifo_size = 1, | |||
| 156 | .tx_loadsz = 1, | |||
| 157 | }, | |||
| 158 | [PORT_8250] = { | |||
| 159 | .name = "8250", | |||
| 160 | .fifo_size = 1, | |||
| 161 | .tx_loadsz = 1, | |||
| 162 | }, | |||
| 163 | [PORT_16450] = { | |||
| 164 | .name = "16450", | |||
| 165 | .fifo_size = 1, | |||
| 166 | .tx_loadsz = 1, | |||
| 167 | }, | |||
| 168 | [PORT_16550] = { | |||
| 169 | .name = "16550", | |||
| 170 | .fifo_size = 1, | |||
| 171 | .tx_loadsz = 1, | |||
| 172 | }, | |||
| 173 | [PORT_16550A] = { | |||
| 174 | .name = "16550A", | |||
| 175 | .fifo_size = 16, | |||
| 176 | .tx_loadsz = 16, | |||
| 177 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |||
| 178 | .flags = UART_CAP_FIFO, | |||
| 179 | }, | |||
| 180 | [PORT_CIRRUS] = { | |||
| 181 | .name = "Cirrus", | |||
| 182 | .fifo_size = 1, | |||
| 183 | .tx_loadsz = 1, | |||
| 184 | }, | |||
| 185 | [PORT_16650] = { | |||
| 186 | .name = "ST16650", | |||
| 187 | .fifo_size = 1, | |||
| 188 | .tx_loadsz = 1, | |||
| 189 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |||
| 190 | }, | |||
| 191 | [PORT_16650V2] = { | |||
| 192 | .name = "ST16650V2", | |||
| 193 | .fifo_size = 32, | |||
| 194 | .tx_loadsz = 16, | |||
| 195 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |||
| 196 | UART_FCR_T_TRIG_00, | |||
| 197 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |||
| 198 | }, | |||
| 199 | [PORT_16750] = { | |||
| 200 | .name = "TI16750", | |||
| 201 | .fifo_size = 64, | |||
| 202 | .tx_loadsz = 64, | |||
| 203 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 | | |||
| 204 | UART_FCR7_64BYTE, | |||
| 205 | .flags = UART_CAP_FIFO | UART_CAP_SLEEP | UART_CAP_AFE, | |||
| 206 | }, | |||
| 207 | [PORT_STARTECH] = { | |||
| 208 | .name = "Startech", | |||
| 209 | .fifo_size = 1, | |||
| 210 | .tx_loadsz = 1, | |||
| 211 | }, | |||
| 212 | [PORT_16C950] = { | |||
| 213 | .name = "16C950/954", | |||
| 214 | .fifo_size = 128, | |||
| 215 | .tx_loadsz = 128, | |||
| 216 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |||
| 217 | .flags = UART_CAP_FIFO, | |||
| 218 | }, | |||
| 219 | [PORT_16654] = { | |||
| 220 | .name = "ST16654", | |||
| 221 | .fifo_size = 64, | |||
| 222 | .tx_loadsz = 32, | |||
| 223 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 | | |||
| 224 | UART_FCR_T_TRIG_10, | |||
| 225 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |||
| 226 | }, | |||
| 227 | [PORT_16850] = { | |||
| 228 | .name = "XR16850", | |||
| 229 | .fifo_size = 128, | |||
| 230 | .tx_loadsz = 128, | |||
| 231 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |||
| 232 | .flags = UART_CAP_FIFO | UART_CAP_EFR | UART_CAP_SLEEP, | |||
| 233 | }, | |||
| 234 | [PORT_RSA] = { | |||
| 235 | .name = "RSA", | |||
| 236 | .fifo_size = 2048, | |||
| 237 | .tx_loadsz = 2048, | |||
| 238 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_11, | |||
| 239 | .flags = UART_CAP_FIFO, | |||
| 240 | }, | |||
| 241 | [PORT_NS16550A] = { | |||
| 242 | .name = "NS16550A", | |||
| 243 | .fifo_size = 16, | |||
| 244 | .tx_loadsz = 16, | |||
| 245 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |||
| 246 | .flags = UART_CAP_FIFO | UART_NATSEMI, | |||
| 247 | }, | |||
| 248 | [PORT_XSCALE] = { | |||
| 249 | .name = "XScale", | |||
| 250 | .fifo_size = 32, | |||
| 251 | .tx_loadsz = 32, | |||
| 252 | .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, | |||
| 253 | .flags = UART_CAP_FIFO | UART_CAP_UUE, | |||
| 254 | }, | |||
| 255 | }; | |||
| 256 | ||||
| 257 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |||
| 258 | ||||
| 259 | /* Au1x00 UART hardware has a weird register layout */ | |||
| 260 | static const u8 au_io_in_map[] = { | |||
| 261 | [UART_RX] = 0, | |||
| 262 | [UART_IER] = 2, | |||
| 263 | [UART_IIR] = 3, | |||
| 264 | [UART_LCR] = 5, | |||
| 265 | [UART_MCR] = 6, | |||
| 266 | [UART_LSR] = 7, | |||
| 267 | [UART_MSR] = 8, | |||
| 268 | }; | |||
| 269 | ||||
| 270 | static const u8 au_io_out_map[] = { | |||
| 271 | [UART_TX] = 1, | |||
| 272 | [UART_IER] = 2, | |||
| 273 | [UART_FCR] = 4, | |||
| 274 | [UART_LCR] = 5, | |||
| 275 | [UART_MCR] = 6, | |||
| 276 | }; | |||
| 277 | ||||
| 278 | /* sane hardware needs no mapping */ | |||
| 279 | static inline int map_8250_in_reg(struct uart_8250_port *up, int offset) | |||
| 280 | { | |||
| 281 | if (up->port.iotype != UPIO_AU) | |||
| 282 | return offset; | |||
| 283 | return au_io_in_map[offset]; | |||
| 284 | } | |||
| 285 | ||||
| 286 | static inline int map_8250_out_reg(struct uart_8250_port *up, int offset) | |||
| 287 | { | |||
| 288 | if (up->port.iotype != UPIO_AU) | |||
| 289 | return offset; | |||
| 290 | return au_io_out_map[offset]; | |||
| 291 | } | |||
| 292 | ||||
| 293 | #else | |||
| 294 | ||||
| 295 | /* sane hardware needs no mapping */ | |||
| 296 | #define map_8250_in_reg(up, offset) (offset) | |||
| 297 | #define map_8250_out_reg(up, offset) (offset) | |||
| 298 | ||||
| 299 | #endif | |||
| 300 | ||||
| 144 | 0 | 301 | static unsigned int serial_in(struct uart_8250_port *up, int offset) | |
| 302 | { | |||
| 303 | offset = map_8250_in_reg(up, offset) << up->port.regshift; | |||
| 304 | ||||
| 305 | switch (up->port.iotype) { | |||
| 0 | - | 306 | case UPIO_HUB6: | |
| 307 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |||
| 0 | - | 308 | return inb(up->port.iobase + 1); | |
| 309 | ||||
| 0 | - | 310 | case UPIO_MEM: | |
| 0 | - | 311 | return readb(up->port.membase + offset); | |
| 312 | ||||
| 0 | - | 313 | case UPIO_MEM32: | |
| 0 | - | 314 | return readl(up->port.membase + offset); | |
| 315 | ||||
| 316 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |||
| 317 | case UPIO_AU: | |||
| 318 | return __raw_readl(up->port.membase + offset); | |||
| 319 | #endif | |||
| 320 | ||||
| 144 | 321 | default: | ||
| 144 | 322 | return inb(up->port.iobase + offset); | ||
| 323 | } | |||
| 324 | } | |||
| 325 | ||||
| 326 | static void | |||
| 222 | 222 | 327 | serial_out(struct uart_8250_port *up, int offset, int value) | |
| 328 | { | |||
| 329 | offset = map_8250_out_reg(up, offset) << up->port.regshift; | |||
| 330 | ||||
| 331 | switch (up->port.iotype) { | |||
| 0 | - | 332 | case UPIO_HUB6: | |
| 333 | outb(up->port.hub6 - 1 + offset, up->port.iobase); | |||
| 334 | outb(value, up->port.iobase + 1); | |||
| 0 | - | 335 | break; | |
| 336 | ||||
| 0 | - | 337 | case UPIO_MEM: | |
| 338 | writeb(value, up->port.membase + offset); | |||
| 0 | - | 339 | break; | |
| 340 | ||||
| 0 | - | 341 | case UPIO_MEM32: | |
| 342 | writel(value, up->port.membase + offset); | |||
| 0 | - | 343 | break; | |
| 344 | ||||
| 345 | #ifdef CONFIG_SERIAL_8250_AU1X00 | |||
| 346 | case UPIO_AU: | |||
| 347 | __raw_writel(value, up->port.membase + offset); | |||
| 348 | break; | |||
| 349 | #endif | |||
| 350 | ||||
| 222 | 351 | default: | ||
| 352 | outb(value, up->port.iobase + offset); | |||
| 353 | } | |||
| 354 | } | |||
| 355 | ||||
| 356 | /* | |||
| 357 | * We used to support using pause I/O for certain machines. We | |||
| 358 | * haven't supported this for a while, but just in case it's badly | |||
| 359 | * needed for certain old 386 machines, I've left these #define's | |||
| 360 | * in.... | |||
| 361 | */ | |||
| 362 | #define serial_inp(up, offset) serial_in(up, offset) | |||
| 363 | #define serial_outp(up, offset, value) serial_out(up, offset, value) | |||
| 364 | ||||
| 365 | ||||
| 366 | /* | |||
| 367 | * For the 16C950 | |||
| 368 | */ | |||
| 0 | 0 | - | 369 | static void serial_icr_write(struct uart_8250_port *up, int offset, int value) |
| 370 | { | |||
| 371 | serial_out(up, UART_SCR, offset); | |||
| 372 | serial_out(up, UART_ICR, value); | |||
| 373 | } | |||
| 374 | ||||
| 0 | 0 | - | 375 | static unsigned int serial_icr_read(struct uart_8250_port *up, int offset) |
| 376 | { | |||
| 377 | unsigned int value; | |||
| 378 | ||||
| 379 | serial_icr_write(up, UART_ACR, up->acr | UART_ACR_ICRRD); | |||
| 380 | serial_out(up, UART_SCR, offset); | |||
| 381 | value = serial_in(up, UART_ICR); | |||
| 382 | serial_icr_write(up, UART_ACR, up->acr); | |||
| 383 | ||||
| 0 | - | 384 | return value; | |
| 385 | } | |||
| 386 | ||||
| 387 | /* | |||
| 388 | * FIFO support. | |||
| 389 | */ | |||
| 6 | 6 | 390 | static inline void serial8250_clear_fifos(struct uart_8250_port *p) | |
| 391 | { | |||
| 6 | 0 | - | 392 | if (p->capabilities & UART_CAP_FIFO) { |
| 393 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO); | |||
| 394 | serial_outp(p, UART_FCR, UART_FCR_ENABLE_FIFO | | |||
| 395 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |||
| 396 | serial_outp(p, UART_FCR, 0); | |||
| 397 | } | |||
| 398 | } | |||
| 399 | ||||
| 400 | /* | |||
| 401 | * IER sleep support. UARTs which have EFRs need the "extended | |||
| 402 | * capability" bit enabled. Note that on XR16C850s, we need to | |||
| 403 | * reset LCR to write to IER. | |||
| 404 | */ | |||
| 6 | 6 | 405 | static inline void serial8250_set_sleep(struct uart_8250_port *p, int sleep) | |
| 406 | { | |||
| 0 | 6 | - | 407 | if (p->capabilities & UART_CAP_SLEEP) { |
| 0 | 0 | - | 408 | if (p->capabilities & UART_CAP_EFR) { |
| 409 | serial_outp(p, UART_LCR, 0xBF); | |||
| 410 | serial_outp(p, UART_EFR, UART_EFR_ECB); | |||
| 411 | serial_outp(p, UART_LCR, 0); | |||
| 412 | } | |||
| 413 | serial_outp(p, UART_IER, sleep ? UART_IERX_SLEEP : 0); | |||
| 0 | 0 | - | 413 | ternary-?: sleep |
| 0 | 0 | - | 414 | if (p->capabilities & UART_CAP_EFR) { |
| 415 | serial_outp(p, UART_LCR, 0xBF); | |||
| 416 | serial_outp(p, UART_EFR, 0); | |||
| 417 | serial_outp(p, UART_LCR, 0); | |||
| 418 | } | |||
| 419 | } | |||
| 420 | } | |||
| 421 | ||||
| 422 | #ifdef CONFIG_SERIAL_8250_RSA | |||
| 423 | /* | |||
| 424 | * Attempts to turn on the RSA FIFO. Returns zero on failure. | |||
| 425 | * We set the port uart clock rate if we succeed. | |||
| 426 | */ | |||
| 427 | static int __enable_rsa(struct uart_8250_port *up) | |||
| 428 | { | |||
| 429 | unsigned char mode; | |||
| 430 | int result; | |||
| 431 | ||||
| 432 | mode = serial_inp(up, UART_RSA_MSR); | |||
| 433 | result = mode & UART_RSA_MSR_FIFO; | |||
| 434 | ||||
| 435 | if (!result) { | |||
| 436 | serial_outp(up, UART_RSA_MSR, mode | UART_RSA_MSR_FIFO); | |||
| 437 | mode = serial_inp(up, UART_RSA_MSR); | |||
| 438 | result = mode & UART_RSA_MSR_FIFO; | |||
| 439 | } | |||
| 440 | ||||
| 441 | if (result) | |||
| 442 | up->port.uartclk = SERIAL_RSA_BAUD_BASE * 16; | |||
| 443 | ||||
| 444 | return result; | |||
| 445 | } | |||
| 446 | ||||
| 447 | static void enable_rsa(struct uart_8250_port *up) | |||
| 448 | { | |||
| 449 | if (up->port.type == PORT_RSA) { | |||
| 450 | if (up->port.uartclk != SERIAL_RSA_BAUD_BASE * 16) { | |||
| 451 | spin_lock_irq(&up->port.lock); | |||
| 452 | __enable_rsa(up); | |||
| 453 | spin_unlock_irq(&up->port.lock); | |||
| 454 | } | |||
| 455 | if (up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) | |||
| 456 | serial_outp(up, UART_RSA_FRR, 0); | |||
| 457 | } | |||
| 458 | } | |||
| 459 | ||||
| 460 | /* | |||
| 461 | * Attempts to turn off the RSA FIFO. Returns zero on failure. | |||
| 462 | * It is unknown why interrupts were disabled in here. However, | |||
| 463 | * the caller is expected to preserve this behaviour by grabbing | |||
| 464 | * the spinlock before calling this function. | |||
| 465 | */ | |||
| 466 | static void disable_rsa(struct uart_8250_port *up) | |||
| 467 | { | |||
| 468 | unsigned char mode; | |||
| 469 | int result; | |||
| 470 | ||||
| 471 | if (up->port.type == PORT_RSA && | |||
| 472 | up->port.uartclk == SERIAL_RSA_BAUD_BASE * 16) { | |||
| 473 | spin_lock_irq(&up->port.lock); | |||
| 474 | ||||
| 475 | mode = serial_inp(up, UART_RSA_MSR); | |||
| 476 | result = !(mode & UART_RSA_MSR_FIFO); | |||
| 477 | ||||
| 478 | if (!result) { | |||
| 479 | serial_outp(up, UART_RSA_MSR, mode & ~UART_RSA_MSR_FIFO); | |||
| 480 | mode = serial_inp(up, UART_RSA_MSR); | |||
| 481 | result = !(mode & UART_RSA_MSR_FIFO); | |||
| 482 | } | |||
| 483 | ||||
| 484 | if (result) | |||
| 485 | up->port.uartclk = SERIAL_RSA_BAUD_BASE_LO * 16; | |||
| 486 | spin_unlock_irq(&up->port.lock); | |||
| 487 | } | |||
| 488 | } | |||
| 489 | #endif /* CONFIG_SERIAL_8250_RSA */ | |||
| 490 | ||||
| 491 | /* | |||
| 492 | * This is a quickie test to see how big the FIFO is. | |||
| 493 | * It doesn't work at all the time, more's the pity. | |||
| 494 | */ | |||
| 0 | 0 | - | 495 | static int size_fifo(struct uart_8250_port *up) |
| 496 | { | |||
| 497 | unsigned char old_fcr, old_mcr, old_dll, old_dlm, old_lcr; | |||
| 498 | int count; | |||
| 499 | ||||
| 500 | old_lcr = serial_inp(up, UART_LCR); | |||
| 501 | serial_outp(up, UART_LCR, 0); | |||
| 502 | old_fcr = serial_inp(up, UART_FCR); | |||
| 503 | old_mcr = serial_inp(up, UART_MCR); | |||
| 504 | serial_outp(up, UART_FCR, UART_FCR_ENABLE_FIFO | | |||
| 505 | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); | |||
| 506 | serial_outp(up, UART_MCR, UART_MCR_LOOP); | |||
| 507 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |||
| 508 | old_dll = serial_inp(up, UART_DLL); | |||
| 509 | old_dlm = serial_inp(up, UART_DLM); | |||
| 510 | serial_outp(up, UART_DLL, 0x01); | |||
| 511 | serial_outp(up, UART_DLM, 0x00); | |||
| 512 | serial_outp(up, UART_LCR, 0x03); | |||
| 0 | 0 | - | 513 | for (count = 0; count < 256; count++) |
| 514 | serial_outp(up, UART_TX, count); | |||
| 515 | mdelay(20);/* FIXME - schedule_timeout */ | |||
| 0 | 0 | - | 515 | ternary-?: ( __builtin_constant_p ( 20 ) && ( .. |
| 0 | 0 | - | 515 | ternary-?: __builtin_constant_p ( ( 20 ) * 100.. |
| 0 | 0 | - | 515 | ternary-?: ( ( 20 ) * 1000 ) > 20000 |
| 516 | for (count = 0; (serial_inp(up, UART_LSR) & UART_LSR_DR) && | |||
| 0 | 0 | - | 517 | (count < 256); count++) |
| 0 | - | 517 | (T) && (T) | |
| 0 | - | 517 | (T) && (F) | |
| 0 | - | 517 | (F) && (_) | |
| 518 | serial_inp(up, UART_RX); | |||
| 519 | serial_outp(up, UART_FCR, old_fcr); | |||
| 520 | serial_outp(up, UART_MCR, old_mcr); | |||
| 521 | serial_outp(up, UART_LCR, UART_LCR_DLAB); | |||
| 522 | serial_outp(up, UART_DLL, old_dll); | |||
| 523 | serial_outp(up, UART_DLM, old_dlm); | |||
| 524 | serial_outp(up, UART_LCR, old_lcr); | |||
| 525 | ||||
| 0 | - | 526 | return count; | |
| 527 | } | |||
| 528 | ||||
| 529 | /* | |||
| 530 | * Read UART ID using the divisor method - set DLL and DLM to zero | |||
| 531 | * and the revision will be in DLL and device type in DLM. We | |||
| 532 | * preserve the device state across this. | |||
| 533 | */ | |||
| 0 | 0 | - | 534 | static unsigned int autoconfig_read_divisor_id(struct uart_8250_port *p) |
| 535 | { | |||
| 536 | unsigned char old_dll, old_dlm, old_lcr; | |||
| 537 | unsigned int id; | |||
| 538 | ||||
| 539 | old_lcr = serial_inp(p, UART_LCR); | |||
| 540 | serial_outp(p, UART_LCR, UART_LCR_DLAB); | |||
| 541 | ||||
| 542 | old_dll = serial_inp(p, UART_DLL); | |||
| 543 | old_dlm = serial_inp(p, UART_DLM); | |||
| 544 | ||||
| 545 | serial_outp(p, UART_DLL, 0); | |||
| 546 | serial_outp(p, UART_DLM, 0); | |||
| 547 | ||||
| 548 | id = serial_inp(p, UART_DLL) | serial_inp(p, UART_DLM) << 8; | |||
| 549 | ||||
| 550 | serial_outp(p, UART_DLL, old_dll); | |||
| 551 | serial_outp(p, UART_DLM, old_dlm); | |||
| 552 | serial_outp(p, UART_LCR, old_lcr); | |||
| 553 | ||||
| 0 | - | 554 | return id; | |
| 555 | } | |||
| 556 | ||||
| 557 | /* | |||
| 558 | * This is a helper routine to autodetect StarTech/Exar/Oxsemi UART's. | |||
| 559 | * When this function is called we know it is at least a StarTech | |||
| 560 | * 16650 V2, but it might be one of several StarTech UARTs, or one of | |||
| 561 | * its clones. (We treat the broken original StarTech 16650 V1 as a | |||
| 562 | * 16550, and why not? Startech doesn't seem to even acknowledge its | |||
| 563 | * existence.) | |||
| 564 | * | |||
| 565 | * What evil have men's minds wrought... | |||
| 566 | */ | |||
| 0 | 0 | - | 567 | static void autoconfig_has_efr(struct uart_8250_port *up) |
| 568 | { | |||
| 569 | unsigned int id1, id2, id3, rev; | |||
| 570 | ||||
| 571 | /* | |||
| 572 | * Everything with an EFR has SLEEP | |||
| 573 | */ | |||
| 574 | up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; | |||
| 575 | ||||
| 576 | /* | |||
| 577 | * First we check to see if it's an Oxford Semiconductor UART. | |||
| 578 | * | |||
| 579 | * If we have to do this here because some non-National | |||
| 580 | * Semiconductor clone chips lock up if you try writing to the | |||
| 581 | * LSR register (which serial_icr_read does) | |||
| 582 | */ | |||
| 583 | ||||
| 584 | /* | |||
| 585 | * Check for Oxford Semiconductor 16C950. | |||
| 586 | * | |||
| 587 | * EFR [4] must be set else this test fails. | |||
| 588 | * | |||
| 589 | * This shouldn't be necessary, but Mike Hudson (Exoray@isys.ca) | |||
| 590 | * claims that it's needed for 952 dual UART's (which are not | |||
| 591 | * recommended for new designs). | |||
| 592 | */ | |||
| 593 | up->acr = 0; | |||
| 594 | serial_out(up, UART_LCR, 0xBF); | |||
| 595 | serial_out(up, UART_EFR, UART_EFR_ECB); | |||
| 596 | serial_out(up, UART_LCR, 0x00); | |||